A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks interconnected by a programmable interconnect network and programmable input/output cells. Programming of the logic blocks, the interconnect resources which make up the network, and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application.
The present inventors have recently developed off-line methods of built-in self-testing the array of programmable logic blocks and the programmable interconnect resources in FPGAs at the device, board and system levels. These methods are set out in detail in U.S. Pat. Nos. 5,991,907, 6,003,150, 6,108,806, and 6,202,182. The full disclosures in these patents are incorporated herein by reference.
In addition to these off-line testing methods, the present inventors have also recently developed methods of testing and fault tolerant operation of the programmable logic blocks and methods of testing the programmable interconnect resources during normal on-line operation of the FPGAs. These testing and operating methods are set out in detail in U.S. Pat. Nos. 6,256,758, 6,550,030, 6,631,487, 6,474,761, and 6,530,049. The full disclosures in these patents are also incorporated herein by reference.
On-line testing and fault tolerant operation of FPGAs is most important in high-reliability and high-availability applications, such as, long-life space missions, telecommunication network routers, or remote equipment in which adaptive computing systems often rely on reconfigurable hardware to adapt system operation to environment changes. In such applications, the FPGA hardware must work continuously and simply cannot be taken off-line for testing, maintenance, or repair.
When faults are detected in the programmable interconnect resources of the FPGA hardware of these systems, the faulty resources must be quickly identified in order to facilitate efficient reconfiguration of the remaining FPGA resources to avoid the faulty resources, or to reuse the faulty resources for fault-tolerant operation of the FPGA. Accordingly, a need is identified for an efficient and adaptive method of identifying faulty programmable interconnect resources which may be performed concurrently with normal system operation or during manufacturing testing.